The present disclosure relates to a video processing circuit and related method thereof, and more particularly, to a processing circuit and related method for merging video output streams with a data stream (e.g. a graphical stream) for transmission.
In a typical digital TV chip application, auxiliary graphics, e.g. on screen display (OSD) information, are usually overlaid on video output streams as user interfaces or user menus. Generally, the graphics and the video output streams are mixed into a single mixed data by a conventional mixer, and the mixed data is then transmitted to a display panel for further display. Please refer to FIG. 1. FIG. 1 is a diagram of a first conventional video processing circuit 100. The video processing circuit 100 includes a video processing chip 110 and a video output device 130, whereof the video processing chip 110 includes a video generating unit 112, an OSD encoder 114, a mixer 116, and a first signal transmitter 118. The generating unit 112 is utilized for generating a video output stream SOUT according to a video input stream SIN. The OSD encoder 114 is utilized for generating an encoded auxiliary graphic data D1. The mixer 116 is coupled to the video generating unit 112 and the OSD encoder 114 for mixing the video output stream SOUT with the graphic data D1 to generate a single mixed data DMIX, and then the first signal transmitter 118 transmits the mixed data DMIX to the video output device 130 through a low voltage differential signal (LVDS) interface. More particularly, the video processing chip 110 is a TV chip installed in a digital TV, and the video output device can be a recorder or a flat panel display (FPD), such as a plasma panel.
In order to enhance video quality, a post-processing chip is necessary for the typical digital TV chip application. Please refer to FIG. 2. FIG. 2 is a diagram of a second conventional video processing circuit 200. In FIG. 2, elements with the same reference numerals as that in FIG. 1 refer to the same elements, and further detailed description is omitted herein for brevity. The difference between the video processing circuit 200 and the video processing circuit 100 is that the video processing circuit 200 further includes a video post-processing chip 220 coupled between the video processing chip 110 and the video output device 130. The video post-processing chip 22 includes a first signal receiver 222, a video post-processing unit 224, and a second signal transmitter 226. The first signal receiver 222 is coupled to the first signal transmitter 118 for receiving the mixed data DMIX, and the video post-processing unit 224 is coupled to the first signal receiver 222 for receiving and post-processing the mixed data DMIX to generate a processed mixed data DPMIX. Then, the second signal transmitter 226 transmits the processed mixed data DPMIX to the video output device 130 through a low voltage differential signal (LVDS) interface.
Due to the video output stream SOUT being mixed with the auxiliary graphic data D1 to generate the mixed data DMIX, both the video output stream SOUT and the graphic data D1 are post-processed by the video post-processing unit 224 by the same scheme for enhancing the video quality thereof. Thus the quality around edges of the graphic data D1 area may be poor as the video enhancement is applied to the mixed data DMIX including contents of the graphic data D1 which replace an overlapped portion within the contents originally carried by the video output stream SOUT and are far different from remaining contents corresponding to the video output stream SOUT.
Please refer to FIG. 3. FIG. 3 is a diagram of a third conventional video processing circuit 300. In FIG. 3, elements with the same reference numerals as that in FIG. 2 refer to the same elements, and further detailed description is omitted herein for brevity. Also, the video processing circuit 300 includes a video processing chip 310, a video post-processing chip 320, and the video output device 130. The differences between the video processing circuit 300 in FIG. 3 and the video processing circuit 200 in FIG. 2 are described in the following. During the operation of the video processing chip 310, the video output stream SOUT and the graphic data D1 are not mixed and are respectively transmitted to the first signal transmitter 118. At this time, only the video output stream SOUT is post-processed by the video post-processing unit 224 to generate a processed video output stream SPOUT for enhancing the video quality. The graphic data D1 is directly transmitted to a mixer 318 without being post-processed by the video post-processing unit 224. Afterwards, the processed video output stream SPOUT and the graphic data D1 are mixed by the mixer 318 to generate a second mixed signal DPMIX2. In this situation, as the whole video contents carried by the video output stream SOUT undergo the video enhancement processing before mixed with the auxiliary graphic data D1, the quality around edges of the graphic data D1 area can be improved but extra I/O pins are needed to transmit the graphic data D1 to the first signal receiver 222.
Presently, most video processing circuits often add a post-processing chip to enhance the video quality. However, if the video output stream SOUT and the graphic data D1 are mixed during the operation of the video processing chip, both the video output stream SOUT and the graphic data D1 are post-processed by the video post-processing chip, resulting in a poor quality around the graphic data D1 area as the mixing process occurs prior to the post-processing process. If the video output stream SOUT and the graphic data D1 are mixed during the operation of the video post-processing chip (i.e., the post-processing process occurs prior to the mixing process), only the video output stream SOUT is post-processed by the video post-processing chip for enhancing the video quality. The disadvantage of this case is that extra I/O pins are needed to transmit the graphic data D1, which is not economical for cost.